`include "timescale.v"

module tb_ahb_ctrl();
reg 		   	  hresetn;
reg 			  hclk;
	
	wire [31:0]  haddr;
	wire [1:0]   htrans;
	wire 		   hwrite;
	wire [2:0]   hsize;
	wire [2:0]   hburst;
	wire [3:0]   hprot;
	wire [31:0]  hwdata;

	// output 		   hsel;

	reg  [1:0]   hresp;
	reg  [31:0]  hrdata; 

	reg 		   LatchTx;						 //the start signal
	
ahb_ctrl U_ahb_ctrl(
  .hresetn(hresetn),
  .hclk(hclk),
	
	.haddr(haddr),
	.htrans(htrans),
	.hwrite(hwrite),
	.hsize(hsize),
	.hburst(hburst),
	.hprot(hprot),
	.hwdata(hwdata),

	// output 		   hsel(),

	.hresp(hresp),
	.hrdata(hrdata), 

	.tx_bd_pointer			(32'h0000_0400),
	.LatchTx(LatchTx)		//the start signal
);

wire 			  hsel ;
assign 			  hsel 		  = 1;
ram_interface(
			  .hresetn(hresetn),
			  .hclk(hclk),
			  .hsel(hsel),	
			  .haddr(haddr),
			  .htrans(htrans),
			  .hwrite(hwrite),
			  .hsize(hsize),
			  .hburst(hburst),
			  .hprot(hprot),
			  .hwdata(hwdata),
			  
			  .hresp(hresp),
			  .hrdata(hrdata) 
);

// always@(posedge hclk or negedge hresetn)
// begin
//   if(!hresetn)
// 	$ahb_ram_init();
//   else 
// 	$ahb_ram(haddr, htrans, hwrite, hsize, hburst, hprot, hwdata, hresp, hrdata);		//sel is not used
// end


initial begin
hclk = 0;
forever #5 hclk = ~hclk;
end

initial begin
hresetn = 0; LatchTx = 0;
#10 hresetn = 1;

#100 LatchTx = 1;
#10 LatchTx = 0;
end

initial begin
hresp = 2'b00;
forever #10 #1 hrdata = $random;
end

endmodule // tb_ahb_ctrl


